1. Field of the Invention
The present invention relates to a semiconductor package, and more particularly, to a semiconductor package using solder balls as external connection terminals.
2. Description of the Related Art
Manufacturing a semiconductor package typically includes a series of operations coupling external connection terminals to a semiconductor chip and sealing the semiconductor chip as a package to protect, for example, against external impact.
Recently as the electronics industry has grown, certain aspects of semiconductor packages have been developed to obtain miniaturization, lightness and reduction in manufacturing cost. Moreover, as semiconductor packages have been applied to digital image devices, MP3 players, mobile phones, massive storage units, etc., various kinds of semiconductor packages have been introduced. For example, a ball grid array (BGA) package and a wafer level chip scale package (WLCSP) are known forms of semiconductor packages.
FIGS. 1 and 2 are cross-sectional views of a conventional BGA package 20 (FIG. 1) and a conventional WLCSP 40 (FIG. 2).
Referring to FIG. 1, in a conventional BGA package, a semiconductor chip 24 is mounted on a printed circuit boaed 22 having printed circuit patterns such as a bond finger 26 and a solder ball pad 36. The bond finger 26 on the printed circuit board 22 is connected to a bond pad 28 on the semiconductor chip 24 by a wire 30. The bond fingers 26 electrically couple by way of the printed circuit board 22 to the solder ball pads 36. Thereafter, a molding process using sealing resin 32 gaurds or encapsulates the semiconductor chip 24 and the wire 30. Lastly, by attaching a solder ball 34 to the solder ball pad 36 on the bottom of the printed circuit board 22, the typical BGA package 20 results.
However, the BGA package 20 has drawbacks relating to the molding process. More particularly, the molding process imposes a minimum thickness limitation because of potential warpage defects. Moreover, it is known to be very difficult to fabricate a BGA package stack, e.g., a stack of BGA packages each having the same or similar structure.
In the case of the general WLCSP 40 shown in FIG. 2, a first insulation layer 48 and a metallic bond pad redistribution pattern 50 are applied to the surface of a semiconductor chip 42 having a bond pad 44 and a passivation layer 46 also formed thereon in a wafer manufacturing process. After a second insulation layer 52 is applied to the surface where the bond pad redistribution pattern 50 is formed, solder ball pads are exposed through a photolithographic process, and solder balls 54 are attached to the solder ball pads.
A minimum thickness of a semiconductor package formed using the WLCSP 40 also exists due to a warpage defect constraint. Also, as with the BGA package 20 (FIG. 1), it is not feasible to fabricate a stacked semiconductor package by using, e.g., stacking, multiple ones of the WLCSP 40. Furthermore, since the semiconductor chip 42 is externally exposed, there is a high risk of cracking, e.g., due to the handling of the semiconductor package.
Presently, a significant concern regarding the WLCSP 40 is the interval between the solder balls 54, e.g., the interval cannot be further decreased due to the international standards established by the Joint Electron Device Engineering Coulcin (JEDEC), even though the size of semiconductor chips has been gradually decreasing through ever greater integration obtained in manufacturing of semiconductor chips. As a result, for example, when the size of a semiconductor chip 42 reduces to two-thirds its original size, one or two solder balls 54 among six solder balls 54 (FIG. 2) cannot be attached to the semiconductor chip 42 according to known BGA packaging methods. In other words, when the solder balls 54 are attached within the footprint of the semiconductor chip 42 as shown in the WLCSP 40, known as a fan-in structure, the density of solder balls 54 cannot match the density of bond pads 44 when the chip 42 reduces to a given size.